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Please use this identifier to cite or link to this item: http://edoc.bseu.by:8080/handle/edoc/85030
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dc.contributor.authorCheremisinova, L.-
dc.date.accessioned2020-11-11T07:54:08Z-
dc.date.available2020-11-11T07:54:08Z-
dc.date.issued2001-
dc.identifier.citationCheremisinova, L. Graph theoretic algorithm for VLSI regular structures folding / L. Cheremisinova // Информационные сети, системы и технологии = Information Networks, Systems and Technologies : в 3 кн. Кн.1 : Труды международной конференции ICINASTe'2001, Минск, 2-4 октября 2001 г. : на англ. яз. / Ред.: А.Н. Морозевич [и др.]. - Мн. : БГЭУ, 2001. - С. 98-102.ru_RU
dc.identifier.isbn985-426-692-3-
dc.identifier.urihttp://edoc.bseu.by:8080/handle/edoc/85030-
dc.description.abstractThe problem under consideration is to reduce the area of the layout of regular VLS structures by means of their folding. Some results of cutting down exhaustive computational efforts on the search for the optimal regular structures folding have been described. An efficient graph theoretic algorithm for one-dimensional unconstrained simple folding is presented.ru_RU
dc.languageАнглийский-
dc.language.isoenru_RU
dc.publisherБелорусский государственный экономический университетru_RU
dc.subjectcomputational costsru_RU
dc.subjectgraph theoreticru_RU
dc.subjectone-dimensional unconstrained simpleru_RU
dc.subjectвычислительные затратыru_RU
dc.titleGraph theoretic algorithm for VLSI regular structures foldingru_RU
dc.typeArticleru_RU
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